Dolby Digital Decoder M65863FP M65863FP M65863FP is a single device. The device decodes AC-3 bitstreams into PCM audio. Dolby Digital (AC-3) is a multi-channel audio coding algorithm developed by Dolby Laboratories, Inc. * Decoding 1) 5.1 ch AC-3 bitstream 2) Dolby Pro Logic*1 encoded 2ch Dolby Digital (AC-3) bitstream 3) Dolby Pro Logic encoded 2ch PCM data * All input combinations from 1 to 5.1 channels * Output : mono 5.1 surround * Sampling rates : 32kHz, 44.1 kHz, 48 kHz and 96 kHz (96 kHz is for linear PCM only) * Supports a maximum bit rate of 640 kbps at a full service (up to 448 kbps when 32 kHz sampling rates) * 2 DIR (Digital Audio Interface Receiver)/ADC input interfaces * Serial input bitstream interface for DEMUX * PCM output interface Standard 3-wire DAC output interface (data,clock,LR clock), 16/18/20/24 bit DAC word size * Supports IEC958 digital audio output for Dolby Digital (AC-3) data stream * I2C*2 interface and clocked serial (4 line) interface for host microcontroller * Generates audio test noise * 2nd DSP I/F (twice higher PCM transfer rate) * Controllable dynamic range compression * Programmable center and surround channel delays * Dialogue level control * No external memory required (M65863FP doos not have memory space for surround delay)M65863FP IEC958 DIR MCU DSP DACM65863FP Configuration Diagram (DIR I/F)M65863FP M65863FP I 2 C/Clocked serial MCUM65863FP M65863FP I/O interface.M65863FP I/O InterfaceM65863FP M65863FP ACLK1 Bit clock input for DIR/ADC input (Line 1). ADATA1 Data input for DIR/ADC interface (Line 1). Latched at the rising edge of ACLK1. ALRCK1 LR clock input for DIR/ADC interface (Line 1). ACLK2 Bit clock input for DIR/ADC input (Line 2). ADATA2 Data input for DIR/ADC interface (Line 2). Latched at the rising edge of ACLK2. ALRCK2 LR clock input for DIR/ADC interface (Line 2) ACLKS Clock for DEMUX interface.M65863FP M65863FP starts detecting sync word when this signal is disabled. SYNCRST request signal which is enabled when M65863FP comes out of synchronization. Audio mute output signal. Output is muted when this signal is enabled (0). This signal is valid for both DIR/ADC interface and DEMUX interface. DOLR PCM output terminal. When control register dspif is 0, L and R channel data are output. When dspif is 1, L, R, C and SW channel data are output. DOCW PCM output terminal. When control register dspif is 0, C and SW channel data are output. When dspif is 1, SL and SR channel data are output. DOSS PCM output terminal. When control register dspif is 0, SL and SR channel data are output. BCLK Bit clock output. LRCK LR clock output. 2BCLK Double-rate bit clock. Used in DSP interface. 2LRCK Double-rate LR clock. Used in DSP interface. CHIPMOD Specifies the chip mode. Decodes the main service when 0, and decodes the associate service when 1. Select decoding of main service when it is not necessary to decode dual streams. CCLK Transmission clock used in data transmission between main and sub chips during dualstream decoding. Sub chip becomes the clock master. This is valid only when control register asmix is 1. CDATA Data transmission line from sub chip to main chip during dual-stream decoding. This is valid only when control register asmix is 1. ASOUT Synchronization signal for dual-stream output. CCLK, CDATA and ASOUT terminals may be open when dual-stream decoding is not required (when control register asmix is 0). MCUSEL Selects which of synchronized serial and I2C is to be used as MCU interface. Synchronized serial is selected when this is 0, and I2C is selected when 1. HSCL/SCK Becomes data transmission clock input in either case of I2C or synchronized serial. HSDA/SI Becomes data input/output terminal in the case of I 2C, and data input terminal in the case of synchronized serial. ADR/SO Becomes chip address selection terminal in the case of I2C, and data output terminal in the case of synchronized serial. _NC/SS Becomes enable signal in the case of synchronized serial. In the case of I 2C, this may be left open because it is not used. MCLKI Audio master clock input. MCLSI [0:1] Indicates whether the audio master clock which is input from MCLKI is 512 fs, 384 fs or 256 fs. Only 384 fs or 256 fs can be selected when the sampling frequency is 96kHz. MCLKO Audio master clock output which gives MCLKI as through-output.M65863FP DIRX Digital audio interface IEC958 input. DOTX Digital audio interface IEC958 output. DEMPH DECSTAT DIRSTATM65863FP M65863FP . In the case, the register addresses for a main chip (which decodes main effect) and those for a sub chip (which decodes associate service) are different. In the following sections, only the register address for a main chip will be shown. For a sub chip you should add h'40 to the corresponding register address for a main chip. For a example, the address of the control register "synclock" is h'14 for a main chip and h'54 for a sub chip. In this may, the address range will be following. Main chip : h'00~h'3f Sub chip : h'40~h'7fM65863FP M65863FP only supports 0 to 8.M65863FP M65863FP M65863FP M65863FP M65863FP M65863FP M65863FP is not decoding. Only read operation is allowed when M65863FP is decoding. address h'12 address h'13 Write Pointer to the Input Data Buffer (writepointer) Write pointer to the input data buffer. Only read operation is allowed.M65863FP M65863FP M65863FP is in the initial state.M65863FP M65863FP becomes the clock master and divides the audio master clock to generate LR clock (LRCK)/bit clock (BCLK). When dacclkmode=1, M65863FP becomes the slave and uses the DIR/ADC input clocks (ALRCK, ACLK) as the LR clock and bit clock, respectively. In the default setting, M65863FP becomes the clock master. Set this value only once when M65863FP is in the initial status.M65863FP M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on/off at any time. Default setting is noise off.M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on/off at any time. Default setting is noise off.M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on/off at any time. Default setting is noise off.M65863FP M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on/off at any time. Default setting is noise off.M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on/off at any time. Default setting is noise off.M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on or off at any time. Default setting is noise off.M65863FP in this field. In the default setting, data stream from DIR/ADC1 is received. This field can be changed at any time.M65863FP receives audio stream from DIR/ADC input 1 M65863FP receives audio stream from DIR/ADC input 2 M65863FP receives audio stream from DEMUX ReservedM65863FP M65863FP M65863FP M65863FP is in the initial status.M65863FP is in the initial status.M65863FP is automatically switched. When the value is 01, the mode is fixed to AC-3 input. When PCM is input in this case, synchronization is lost and the output is muted. When the value is 10 or 11, the mode is fixed to PCM input, except that value 10 causes sync preamble to be searched and, when sync preamble is detected, causes the output to be muted. When the value is 11, sync preamble is not searched. Therefore, mistaken input of AC-3 stream results in its output as it is. Default value is 00 (automatic judgment of AC-3/PCM). This field can be set at any time.M65863FP M65863FP uses the default coefficient value. When it is 1, value of control register (address IE-33) is used in karaoke mixing. Default value is 0. While this field can be changed at any time, set value is reflected in synchronization with the audio block during Dolby Digital (AC-3) decoding. Karaoke Capable Default Vocal (kcapdef) 2 bits This field indicates the vocal reproduction when the default coefficient value is used in karaoke capable mode. Default value is 00. While this field can be changed at any time, set value is reflected in synchronization with the audio block during Dolby Digital (AC-3) decoding.M65863FP M65863FP starts to mute output when the field is changed to 1 and finishes muting when the field is changed to 0. Default value is 1 (mute on). While this field can be changed at any time, set value is reflected at the beginning at a new audio block.M65863FP inputs Dolby Digital (AC-3) stream for exactly 1 frame at a time. When the field is '0', M65863FP inputs Dolby Digital (AC-3) stream until the input buffer is full. Default value is '0'. Set the value in the field only once when M65863FP is in the initial state. Copy Right Bit (copyrightb) 1 bit The value in this filed is written in the "copyrightb" field in IEC958 when using DEMUX I/F. IEC958 Data Stream Number Selection (istrnums) 3 bits M65863FP decodes the data stream whose number is same as this field. Default value is b'000. Set value in the field is reflected at the beginning at a new audio frame. address h'21 Category Code (catecode) 8 bits Value specified in this field is written in the category code field of the channel status word of IEC958 output. Default value is h'00. This field can be set at any time. address h'22 address h'23 Karaoke Mixing Coefficient (kcoeffa) 16 bits Coefficient for mixing V1 with Lk. Value h'7FFF corresponds to 1.0. Default value is h'0000 (0.0). While this field can be changed at any time, set value is reflected in synchronization with the audio block during Dolby Digital (AC-3) decoding. address h'24 address h'25 Karaoke Mixing Coefficient (kcoeffb) 16 bits Coefficient for mixing V2 with Lk. Value h'7FFF corresponds to 1.0. Default value is h'0000 (0.0). While this field can be changed at any time, set value is reflected in synchronization with the audio block during Dolby Digital (AC-3) decoding. address h'26 address h'27 Karaoke Mixing Coefficient (kcoeffc) 16 bits Coefficient for mixing M with Lk. Value h'7FFF corresponds to 1.0. Default value is h'0000 (0.0). While this field can be changed at any time, set value is reflected in synchronization with the audio block during Dolby Digital (AC-3) decoding. address h'28 address h'29 Karaoke Mixing Coefficient (kcoeffd) 16 bits Coefficient for mixing V1 with Ck. Value h'7FFF corresponds to 1.0. Default value is h'0000 (0.0). WhileM65863FP M65863FP M65863FP M65863FP and Digital Audio I/F Receiver or A/D converter consists of the signals ACLK, ADATA, ALRCK as follows (see figure 5.1). M65863FP supports 3 kinds of input formats(MSB first right-justified, LSB first right-justified and I2S) and 4 word sizes(16, 18, 20 and 24bit).M65863FP M65863FP The input format can be chosen among MSB first right-justified format , LSB first right-justified format and I2S format with the control register 'dirformt'(address h'15). Also, the word size can be chosen among 16, 18, 20 and 24bit with the control register 'inbitlen' (address h'17). The relationship between the signal level of ALRCK and output channel (L/R, C/SW, SL/SR) is selective. The details are shown in figure 5.2 and figure 5.3. When M65863FP accepts Dolby Digital (AC-3) data from Digital Audio I/F Receiver, 16 bit mode must be selected.M65863FP M65863FP M65863FP consists of the signals ACLKS, ADATAS, ADVLDS, _ADREQ, SYNCRST and RSYNCREQ as follows (see figure 5.4).M65863FP M65863FP When M65863F accepts AC-3 data from MPEG2 System decoder (DEMUX), the protocol is shown in figure 5.5.M65863FP If burstcont is a 0, _ADREQ will be high when the input buffer becomes full. If burstcont is a 1, _ADREQ will be high when M65863FP relieves 1 sync frame. The burstcont returns to low when M65863FP outputs the first PCM of the frame.M65863FP returns to the state of being out of synchronization. Operation when SYNCRST is asserted varies depending on the value of control register syncrsten. When syncrsten = 01 (mode A) While SYNCRST is asserted, detection of sync word is not carried out with out-of-sync status persisting, and AC-3 stream is not stored in the input buffer. When SYNCRST is negated, M65863FP begins detection of sync word and, when sync word is detected, transfers the AC-3 stream to the input buffer and restarts decoding. When syncrsten = 10 (mode B) When SYNCRST is asserted, M65863FP enters out-of-sync status and, at the same time, begins detection of sync word and, when sync word is detected, transfers the AC-3 stream to the input buffer. InM65863FP M65863FP restarts decoding at the nearest frame behind the address indicated by Read Pointer of the input buffer. Therefore, any desired frame which is input during assertion period and the subsequent data can be played back, by writing over the Read Pointer during assertion period. In the period when SYNCRST is asserted, M65863FP processes AC-3 stream input and overwrites the contents of the buffer even if the input buffer overflows.M65863FP fails to detect sync word twice successively, M65863FP is determined to be out of synchronization. M65863FP sets the RSYCREQ pin and "synccon" (status register) to 1 and mutes the output. "synccon" remains to be 1 until M65863FP is locked in synchronization. RSYCREQ changes to 0 when M65863FP detects sync word next time.M65863FP mutes the output signal when _AMUTE becomes 0. _AMUTE can be asserted or negated asynchronously. However, M65863FP starts/ends muting in the next synchronization frame when assert/negate signal is received.M65863FP can reestablish synchronization by using the external terminal SYNCRST as follows. As mentioned in 5.1.3, operation varies depending on whether the control register syncrsten is 01 or 10. In the case of mode A (control register syncrsten is 01) 1) SYNCRST is asserted. 2) When M65863FP detects rising edge of SYNCRST, M65863FP comes out of synchronization and asserts RSYCREQ. In the case of mode A, M65863FP does not detect sync word and remains out of synchronization while SYNCRST is enabled. When M65863FP is out of synchronization, input stream is not stored in the input buffer. 3) When M65863FP detects rising edge of SYNCRST, it starts detection of sync word. 4) When M65863FP detects sync word, it stores input stream in the input buffer and starts decoding. RSYCREQ is negated at this time. When an internal cause necessitates it to establish synchronization again, M65863FP requests DEMUX to assert SYNCRST by asserting RSYCREQ (Second SYNCRST and RSYCREQ in Figure 5.6).M65863FP M65863FP In the case of mode B (control register syncrsten is 10) 1) SYNCRST is asserted. 2) When M65863FP detects rising edge of SYNCRST, M65863FP comes out of synchronization and asserts RSYCREQ. In the case of mode B, M65863FP inputs Dolby Digital (AC-3) stream and searches for sync word even when SYNCRST is enabled. 3) When M65863FP detects sync word, it negates RSYCREQ and stores Dolby Digital (AC-3) stream in the internal input buffer. It should be noted, however, that decoding is not restarted under this condition. 4) When M65863FP detects the falling edge of SYNCRST, it restarts decoding at the nearest audio frame behind the address indicated by Readpointer. In mode B, decoding can be restarted at any desired audio frame which is input after assertion of SYNCRST, by writing over the Readpointer for the input buffer during the period of asserting SYNCRST (It is limited to the frame following the detection of sync word and restart of transfer to the input buffer.). When an internal cause necessitates it to establish synchronization again, M65863FP requests DEMUX to assert SYNCRST by asserting RSYCREQ.M65863FP M65863FP carries out audio output in the format of DAC interface shown in 5.2.1 or DSP interface shown in 5.2.2. Selection from among these formats is made by means of the control register dspif. DAC interface is selected when dspif is 0, and DSP interface is selected when dspif is 1.M65863FP transmits PCM data via standard 3 line interface (data, sampling clock and clock) for DAC. M65863FP supports 3 formats (MSB first right-justified, LSB first right-justified and I2S) and 4 DAC word sizes (16, 18, 20 and 24 bit). While 24 bit output can be selected also in the case of AC-3 decoding, effective accuracy is limited to 20 bits. BCLK is a clock having frequency 64 times that of LRCK, where DO changes at the falling edge of BCLK. An example of I2S format is shown in figure 5.7 and an example of right-justified format is shown in figure 5.8. The relation of LRCK level and L/R, C/SW and SL/SR outputs can be changed by setting the MSB of dacform. If MSB of dacform is 0, PCM data of the left channel, center channel and surround left channel are output from 3 lines of output are output when LRCK is 1. When LRCK is 0, PCM data of the right channel, sub woofer and surround right channel are output. The above relation is inverted when MSB of dacform is 1. LRCK and BCLK can be either generated by M65863FP by dividing the audio master clock (master mode), or taken from inputs of DIR/ADC interfaces (slave mode). Setting dacclkmode to 0 results in master mode and setting it to 1 results in slave mode.M65863FP and DACM65863FP M65863FP and DACM65863FP by dividing the audio master clock (master mode), or taken from the input of DIR/ADC interface (slave mode). Setting the control register dacclkmode to 0 results in master mode and setting it to 1 results in slave mode. This output is suitable for the output of audio data to DSP which has only 2 lines of data input.M65863FP and DAC(dacform[0]=0)M65863FP M65863FP and DAC(dacform[0]=1)M65863FP outputs either of 2 input data streams from DOTX. The selection of the input data streams desponds on the content of inportsel(Control register). 1) When inportsel(control register) is 00 or 01 (DIR I/F input), M65863FP bypasses the input stream from DIRX to DOTX. 2) When inportsel(control register) is 10 (DEMUX I/F input), M65863FP formats the input data stream in IEC958(S/PDIF) and outputs it. Table 5.1 and figure 5.11 show the format of consumer mode and the format for consumer digital audio products, respectively. Table 5.1 Format of IEC958 (S/P DIF) Consumer ModeM65863FP M65863FP M65863FP M65863FP supports I 2C and clocked serial I/F for MCU I/F, You can chose one of them with Pin 'MCUSEL'. When MCUSEL=1, I2C is selected. When MCUSEL=0, clocked serial I/F is selected. In either case, M65863FP works as a slave.M65863FP by using I2C bus.M65863FP : "0011110"M65863FP (slave).M65863FP (slave) RegisterM65863FP M65863FP .M65863FP (slave) Register Multiple-byte accessing operation: In this operation, M65863FP sends data in order to host micro. Figure 5.17 shows an example of a packet where the host micro continues reading from the M65863FP .M65863FP (slave) Register Continuously General Call addressing: The M65863FP supports a subset of the general call address. When M65863FP (AD3) receives "00000110" described in figure 5.18 after a general call address, M65863FP resets the programmable register after STOP condition is detected.M65863FP M65863FP takes in 8 byte data which remains in the buffer (shift register) at the time _SS is enabled. In the case of data output, 1 byte data following the clock immediately after _SS was enabled is output. Data input SI is latched at the falling edge of clock SCLK, and data output SO is output at the rising edge of clock SCLK. Also when _SS is disabled, M65863FP ignores the input from SI and the SCK clock, while Hi-Z is output from SO.M65863FP M65863FP M65863FP M65863FP M65863FP to a Master When reading from M65863FP , specify in the 1 byte the start address of reading (7 bits) following 0 (1 bit) which indicates reading operation, and specify in the 2 byte the number of bytes to be read. M65863FP outputs data according to the clock from MCU that follows. M65863FP When writing into M65863FP , specify in the 1 byte the start address of writing (7 bits) following 1 (1 bit) which indicates writing operation, and specify in the 2 byte the number of bytes to be written. Thereafter, specified number of bytes of data to be written is transmitted. * 7M65863FP M65863FP M65863FP M65863FP chips. In this case, set asmix (control register) to High on both chips and specify chip mode(mainchip or subchip) on either chip with Chipmode(control register). Main chip and sub chip decode main effect and associate service respectively. The Main chip and Sub chip communicate with each other in the following manner.M65863FP M65863FP Set operation mode Cancel muting : Status of M65863FP *1 : M65863FP changes through plural states according to the operation mode and sync lock/presence of error (See section 6.5 for detail).M65863FP enters the initial state by executing the initialization routine. In the initial state, all control registers are set to their default values. When the initialization routine has completed, set the external interface and operation mode by writing over the values of the control registers. Unless otherwise stated, external interface can be set only once immediately after resetting. In the initial state, output is automatically muted because the control register muteonoff is 1. When the external interface and decoding mode have been set, set the control register muteonoff to 0 and enable the PCM output. When locked in synchronization and it is verified that the transmitted data has no error, M65863FP carries out decoding according to the operation mode and outputs PCM. When an error such as out-of-sync andM65863FP M65863FP mutes the output. Some of external interfaces and operation mode can be changed even while decoding. When changing external interface, however, mute the output by using the control register muteonoff or external terminal _AMUTE. When changing the operation mode, on the other hand, M65863FP automatically mutes the output.M65863FP executes the initialization routine to set default values in the on-chip registers. The initialization routine takes 0.2msec. Upon completion of the initialization routine, set the external interface and decoding mode by writing over the values of the control registers.M65863FP M65863FP is running. 1) Selection of input port Control register : inportsel Option : 2) Selection of input bit length Control register : inbitlen Option : 16 bit, 18 bit, 20 bit, 24 bit 3) AC-3/PCM input mode in DIR I/F Control register : dirdatamode Option : Automatic judgment of AC-3/PCM, fixing to AC-3, fixing to PCM (w/mute), fixing to PCM (w/o mute) 4) Decoding stream number in DIR I/F Control register : istmums Option : b'000 - b'111 5) Selection of input format in the case of DIR/ADC Control register : dirform Option : I2C, MSB first right-justified, LSB first right-justified 6) Selection of output mode Control register : dspif Option : DAC I/F, DSP I/F 7) Selection of output format Control register : dacform Option : I2C, MSB first right-justified, LSB first right-justified 8) Output bit length Control register : outbitlen Option : 16 bit, 18 bit, 20 bit, 24 bit If you want to change the above settings during PCM output, mute the output by using the control register muteonoff or external terminal _AMUTE. Items which can be set only once immediately after resetting 1) Selection of LRCK/BCLK mode Control register : dacclkmode Option : Generation by M65863FP (master), use of input ALRCK, ACLK (slave) 2) Whether dual stream decoding or not Control register : asmix Option : Single stream decoding, dual stream decoding 3) Number of sync words required before sync-lock Control register : synclock Option : 1 to 7 4) Input mode in the case of DEMUX I/F Control register : burstcont Option : Input till buffer-full, input frame by frame 5) Selection of SYNCRST function in the case of DEMUX I/F Control register : syncrsten Option : No use of SYNCRST, SYNCRST mode A, SYNCRST mode BM65863FP M65863FP supports the following operation modes. Mode varies depending on the setting of control register and the input stream. Operation mode can be changed even during PCM output by M65863FP . When changing the mode, M65863FP automatically mutes the output to prevent abnormal sound. 1) Dolby Digital (AC-3) + Pro Logic decoding mode This mode is achieved when the following 2 conditions are satisfied. a) Control register dirdatamode is 00 and AC-3 input is affirmed or control register dirdatamode is 01. b) Control register pdecmode is 01, or pdecmode is 10 and dsumode in the input AC-3 stream is 10. 2) Dolby Digital (AC-3) decoding mode This mode is achieved when the following 2 conditions are satisfied. a) Control register dirdatamode is 00 and AC-3 input is affirmed, or control register dirdatamode is 01. b) Control register pdecmode is 00, or pdecmode is 10 and dsumode in the input AC-3 stream is other than 10. 3) PCM + Pro Logic decoding mode (on/off switching of de-emphasis process enabled) This mode is achieved when control register dirdatamode is 00 and PCM input is affirmed, or when control register dirdatamode is either 10 or 11 and control register pdecmode is 01. Pro Logic decoding mode can further be changed by means of control registers autobal and narwid. Deemphasis can be switched on/off by means of control register dempha and external terminal DEMPHA. 4) PCM through mode (on/off switching of de-emphasis process enabled) This mode is achieved when control register dirdatamode is 00 and PCM input is affirmed, or when control register dirdatamode is either 10 or 11 and control register pdecmode is 00. De-emphasis can be switched on/off by means of control register dempha and external terminal DEMPHA. 5) Noise output mode This mode is achieved by setting a value 1 in any of control registers (lnoise, cnoise, rnoise, srnoise, slnoise, swnoise). Only the operation mode 1, 2 and 5 are supported in the case of DEMUX I/F. When control register dirdatamode is 00, AC-3/PCM is automatically determined which is carried out by searching IEC958sync preamble. M65863FP outputs the current status (AC-3 input/PCM input) through the external terminal DIRSTAT. For details, refer to the description on control register dirdatamode in section 4.4. The following settings can be done in Dolby Digital (AC-3) decoding mode. 1) Number of output channels Control register : outchmode Option : 1ch to 5ch 2) Output during dual monaural mode Control register : stereo Option : Output of ch1 only, output of ch2 only, output of ch1 from Lch and ch2 from Rch, output of ch1+ch2 3) Compression mode Control register : compmod Option : RF mode, LINE mode, custom A, custom B 4) Dynamic range compression scaling Control register : hcompsc, lcompsc Option : No compression (h'00) to Full compression (h'7f)M65863FP M65863FP takes the following states during Dolby Digital (AC-3) decoding. Current status can be checked by means of the status register and external terminal. For detail, refer to 3. Input/output pins and 4.3 Status register. 1) Out-of-sync status State of being out of synchronization. Output is muted. In this state, when sync word is successfully detected successively the number of times specified in the control register synclock, M65863FP enters the normal decoding status. 2) Sync lock & muting status A state in which output is muted because, although synchronization is established, an error was detected in external direction (external terminal AMUTE, control register muteonoff) or in the stream. M65863FP enters the normal decoding status when the external direction is canceled or the error in the stream is removed. When detection of sync word fails twice successively, on the contrary, M65863FP comes out of synchronization. When control register syncrsten is 01 or 10, assertion of external terminal SYNCRST also results in the status of out of synchronization. 3) Normal decoding status A state of decoding normally carried out with PCM being output. This state is achieved if synchronization is locked and no error is detected in the data stream. When detection of sync word fails 2 successively in this state, M65863FP comes out of synchronization. When control register syncrsten is 01 or 10, assertion of external terminal SYNCRST also results in the status of out of synchronization. M65863FP autonomously changes through the above states except for the operations of the external terminal SYNCRST.M65863FP M65863FP mutes the output PCM. Specifically, muting operation is carried out in the following cases. 1) CRC1/CRC2 error and encode error are detected during Dolby Digital (AC-3) decoding. Encode error refers to a case when an abnormal value is detected in bitstream in spite of normal result of CRC check. 2) sync preamble is detected when control register dirdatamode is 10 and PCM input is under way. 3) External terminal AMUTE is asserted. 4) Control register muteonoff is 1. Mute ON/mute OFF operation when decoding Dolby Digital (AC-3) is carried out by using 256 samples by means of the window function defined in Dolby Digital (AC-3).M65863FP M65863FP varies between the cases of DIR I/F input and DEMUX I/F input. Decoding delay is given by the following equation. Decoding delay = 1 frame transmission time * 2/3 + 1 audio block period For example, when sampling frequency is 48kHz and bit rate of stream data is 384 kbps (length of 1 frame is 768*16 bits), decoding delay becomes approx. 11ms because the two terms in the above equation have the following values. Transmission time of 1 frame : (768*16)/(48000*32)*2/3 = 5.3msec 1 audio block period : 256/48000 = 5.3msec Decoding delay in the case of DEMUX I/F is different from the case of DIR I/F, because PCM output and IEC958 output of AC-3 stream are synchronized. In the case of DEMUX I/F mode B, decoding delay is different from the cases of other modes, because it is assumed that AC-3 stream has already been input to the input buffer in this case. When in mode A Decoding delay = 1 frame transmission time + 1 audio block period For example, when sampling frequency is 48kHz and AC-3 stream is continuously transmitted, decoding delay becomes approx. 37msec. Transmission time of 1 frame : 1536/48000 = 32msec 1 audio block period : 256/48000 = 5.3msec When in mode B Decoding delay = 1 audio block period In the case of Dolby Digital (AC-3) decoding, M65863FP does not support surround/center delay. In the case of Pro Logic decoding, surround delay is fixed at 15ms.M65863FP M65863FP M65863FP allows it to form oscillation circuit and a frequency quadruplier (PLL) circuit by connecting an oscillator element, resistor and capacitor on the outside. This enables it to generate the clock required for the internal operation, though auto-oscillation by using low-frequency external clock.M65863FP PLL2 PLL1 PCLK PVCO PLLGNDM65863FP M65863FP M65863FP M65863FP M65863FP Typical ConfigurationM65863FP ) 1) All or part of DEMUX, ADC and DIR can be connected to M65863FP as audio inputs. 2) 2nd DSP assumes processes such as center/surround delay and crossover filter to be done. When limited to AC-3 2ch output, output of M65863FP can be directly connected to DAC. 3) MCU I/F supports I2C I/F as well as the above (synchronized 4 line serial). 4) While M65863FP functions as clock master with respect to LRCK/BCLK of 2nd DSP and DAC, such an application is possible as M65863FP functions as slave while ALRCK and ACLK from DIR/ADC are supplied to 2nd DSP and DAC.M65863FP M65863FP M65863FP M65863FP M65863FP M65863FP M65863FP
